By Topic

Reducing power consumption during TLB lookups in a PowerPC™ embedded processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
S. Swaminathan ; IBM Microelectron., Research Triangle Park, NC, USA ; S. B. Patel ; J. Dieffenderfer ; J. Silberman

We present a microarchitectural-level low-power translation lookaside buffer (TLB) design for embedded system applications. High-performance embedded processors with small micro-TLBs frequently encounter a large number of micro-TLB misses and many types of context switches such as internal and external interrupts. Context switches flush the micro-TLBs and therefore cause a number of unified-TLB accesses for address translation. Our method presents a microarchitecture wherein the power dissipation associated with unified-TLB accesses is minimized. In addition, our technique enables large process ID register sizes which can reduce the operating system software overhead. Our experiments using specINT 2000 benchmarks show that we obtain an average power saving of 36% in the content addressable memory (CAM) comparisons for these accesses.

Published in:

Sixth international symposium on quality electronic design (isqed'05)

Date of Conference:

21-23 March 2005