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A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

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5 Author(s)
E. S. Sundar ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Madras, India ; V. Chandrasekhar ; M. Sashikanth ; V. Kamakoti
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This work proposes a new CLB architecture for FPGAs that can detect and correct single event upset (SEU) faults in the LUTs. A methodology for mapping logical functions onto the LUTs is presented that exploits the features of the proposed CLB architecture to detect and correct the SEU faults in the LUTs. Experimental results obtained by mapping standard benchmark circuits on the proposed architecture indicate that on an average, 96% of the SEU in the LUTs can be detected without employing any redundancy. Further, by using duplication with comparison (DWC) techniques it is shown that 100% of the SEU in the LUTs can be detected for any circuit that is mapped on the proposed architecture; and for the benchmark circuits, on an average, 96% of the SEU in the LUTs can be automatically (without any user intervention or reconfiguration) corrected.

Published in:

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Date of Conference:

6-8 Dec. 2004