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Reliability analysis for defect-tolerant nano-architectures in the presence of interconnect noise

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2 Author(s)
D. Bhaduri ; Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; S. K. Shukla

Recently, we have automated a computational scheme based on Markov random field (MRF) and belief propagation algorithms in a tool code named NANOLAB to evaluate reliability of nano architectures. In this paper, we show how we extend this tool by developing libraries that automate the reliability analysis of systems in the presence of noise in the interconnects. The effectiveness of this automation is illustrated by modeling uniform and Gaussian noise and automatically deriving various reliability results for defect-tolerant architectures, such as triple modular redundancy (TMR), cascaded triple modular redundancy (CTMR) and multi-stage iterations of these. These results are used to interpret reliability/redundancy tradeoffs for these architectural configurations taking into account such noise models at the interconnects.

Published in:

Nanotechnology, 2004. 4th IEEE Conference on

Date of Conference:

16-19 Aug. 2004