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SPIN-TEST: automatic test pattern generation for speed-independent circuits

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2 Author(s)
Feng Shi ; Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA ; Makris, Y.

SPIN-TEST is a simulation-based gate-level ATPG system for speed-independent circuits. Its core engine is an A* search algorithm which employs an accurate fault simulator and an efficient cost function to guide a deterministic test pattern generation phase. A random test pattern generation phase is also available in order to improve run time. The key ATPG challenge in speed-independent circuits is the generation of patterns that are valid independently of the relative timing and the order of arrival of signals. SPIN-TEST addresses this challenge by guaranteeing fault sensitization with hazard/race-free patterns and response observation that is not affected by oscillations or non-deterministic circuit states. Experimental results on benchmark circuits demonstrate the efficiency of SPIN-TEST in terms of both high fault coverage and low test generation time.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004

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