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Techniques for improving the accuracy of geometric-programming based analog circuit design optimization

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4 Author(s)
Jintae Kim ; Dept. of Electr. Eng., Californica Univ., Los Angeles, CA, USA ; Jaeseo Lee ; Vandenberghe, L. ; Yang, C.-K.K.

We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the results from optimization and simulation, and propose several methods to reduce the error. Device modeling based on convex piecewise-linear (PWL) function fitting is introduced to create accurate active and passive device models. We also show that in selected cases GP can enable nonconvex constraints such as bias constraints using monotonicity, which help reduce the error. Lastly, we suggest a simple method to take the modeling error into account in GP optimization, which results in a robust design over the inherent errors in GP device models. Two-stage operational amplifier and on-chip spiral inductor designs are given as examples to demonstrate the presented ideas.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004

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