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Banked scratch-pad memory management for reducing leakage energy consumption

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4 Author(s)
Kandemir, M. ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; Irwin, M.J. ; Chen, G. ; Kolcu, I.

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. We propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004