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A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing synapses. The results of the operations are evaluated by both experiments and simulation program with integrated circuit emphasis (SPICE).
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on (Volume:4 )
Date of Conference: 25-29 July 2004