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Pipelined array-based FIR filter folding

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4 Author(s)
P. Bougas ; Fac. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece ; P. Kalivas ; A. Tsirikos ; K. Z. Pekmestzi

The elaborate design of folded finite-impulse response (FIR) filters based on pipelined multiplier arrays is presented in this paper. The design is considered at the bit-level and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware complexity. Both direct and transposed FIR filter forms are considered. The carry-save and the carry-propagate multiplier arrays are studied for the filter implementations. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the pipelined Wallace Tree multiplier. The comparison reveals that the proposed schemes require 20%-30% less hardware. Finally, efficient implementation of partially folded FIR filter circuits is presented when constraints in area, power consumption and clock frequency are given.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:52 ,  Issue: 1 )