By Topic

Effect of jitter on asynchronous sampling with finite number of samples

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Da Dalt, N. ; Mixed Signal Dept., Design Center, Villach, Austria

In modern communication systems, the conversion of analog signals into digital form [analog-digital conversion (ADC)] is one of the most critical functions. A fundamental limit of the signal-to-noise ratio (SNR) achievable in this conversion is given by the jitter of the sampling clock. The requirements on the maximum jitter tolerable are typically specified using SNR expressions which hold in the case of an infinite number of samples. However, there are good reasons to investigate the resulting SNR when only a finite number of samples is taken into account. This paper evaluates the effective impact of jitter on the SNR of the ADC process when the observation interval is limited to a finite number of samples. It will be shown that, in this case, the jitter constraints on the sampling clock can be more relaxed.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:51 ,  Issue: 12 )