Referenced Items are not available for this document.
The proposed design demonstrates a new high-speed, low-power methodology in a 32 Kb SRAM cache. A fast cycle time of up to 3 GHz is accomplished by using pipelined asynchronous decoders along with a parallel local/global decoding scheme. Power consumption is minimized by using current mode reads and writes throughout the design. The resulting cache operates with an average power dissipation of 390mW at 2GHz in 1.8V, 0.18μm bulk CMOS technology.
Published in:
SOC Conference, 2004. Proceedings. IEEE International
Date of Conference: 12-15 Sept. 2004
- Page(s):
- 251 - 254
- Print ISBN:
- 0-7803-8445-8
- INSPEC Accession Number:
- 8169724
- Digital Object Identifier :
- 10.1109/SOCC.2004.1362425
- Product Type:
- Conference Publications
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