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An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18μm process, at which the average error is within 7% between our formulation and HSPICE.
SOC Conference, 2004. Proceedings. IEEE International
Date of Conference: 12-15 Sept. 2004