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Soft-errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by electrical noise or high-energy particle strikes. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits in the near future. Existing circuit and architectural solutions are inadequate because they have appreciable area/cost, performance, and/or power overheads. We present a very efficient and systematic error-masking technique for static CMOS combinational circuits that prevents an SET pulse, with width, in the worst case, less than approximately half of the timing slack available in its propagation path, from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-efficient manner, which makes this technique applicable to commodity as well as reliability-critical applications. Application of this technique to ISCAS85 benchmark circuits yields average soft-error rate reduction of 75.71% with average area overhead of only 18.14%.