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In this work, the implementation of a high speed analog-to-digital converter (ADC) for SONET OC-192 is discussed. Following a system level analysis, it is shown that in CMOS technology the sample and hold circuit represents one of the main bottleneck for implementing an ADC for this application. To satisfy SONET requirements a CMOS sample and hold circuit is proposed that can be used to implement a 6 bit 10 GS/s interleaved ADC.
SOC Conference, 2004. Proceedings. IEEE International
Date of Conference: 12-15 Sept. 2004