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A semi-digital delay-locked loop using an analog-based finite state machine

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3 Author(s)
Woogeun Rhee ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Parker, B. ; Friedman, D.

This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semi-digital DLL in 0.12-μm CMOS exhibits less than 10-12 bit error rate at 3.2 Gb/s consuming 60 mW.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:51 ,  Issue: 11 )

Date of Publication:

Nov. 2004

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