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Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell. A transceiver chip was designed in 0.13 μm CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a three-level return-to-null signaling scheme with simultaneous voltage and timing reference extraction, to minimize the hardware costs and achieve robust operation for sending update information from receiver to the transmitter. The measured results indicate that this backchannel achieves reliable communication without noticeable impact on the forward link for bandwidths up to 50MHz and swings of 20-100mV.