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A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 μm2 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.
Date of Conference: 17-19 June 2004