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A six phases LC based ring oscillator for 1.5-3Gbit/s SATA interface

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5 Author(s)
R. Tonietto ; Dipt. di Elettronica, Pavia Univ., Italy ; I. Bietti ; B. Mercier ; R. Marbot
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A 3 GHz six phases PLL clock synthesizer embedded in a complete Serial Advanced Technology Attachment (SATA) standard compliant oversampling PHY is presented. Multiphase frequency synthesis has been realized using an LC ring structure VCO, featuring improved phase noise and phase accuracy. Integrated in a standard 0.13 μm CMOS process the synthesizer has an active area of 0.8 mm2 and consumes 35 mW while achieving a phase noise of -120dBc/Hz @ 1MHz and a maximum measured phase error of 0.3°. In addition a novel analytical method to investigate the phase accuracy properties of LC ring structures is presented and validated through simulations.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004