By Topic

VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. Hariyama ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; M. Kameyama

This paper presents a VLSI processor for reliable stereo matching to establish correspondence between images by selecting a desirable window size for sum of absolute differences(SAD) computation. In SAD computation, a degree of parallelism between pixels in a window changes depending on its window size, while a degree of parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is also proposed to achieve 100% utilization of processing elements. Not only 100% utilization but also a simple interconnection network between memory modules and processing elements makes the VLSI processor much superior to the pixel-parallel-architecture-based VLSI processors.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004