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A 4GHz Fractional-N synthesizer for IEEE 802.11a

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7 Author(s)

Phase noise of the Fractional-N synthesizer depends critically on the linearity of its building blocks. In this research, new design methods are shown to directly improve its linearity. This includes a new re-timing scheme that effectively reduces phase noise for multi-modulus dividers. Further reductions in phase noise result from introduction of a high linearity CMOS charge pump. Measurement results verify the concept and demonstrate low phase noise performance at 4GHz.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

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