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Performance comparison of load/store and symmetric instruction set architectures

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3 Author(s)
Alpert, D. ; Nat. Semicond. Israel, Herzelia, Israel ; Averbuch, A. ; Danieli, O.

Two pipeline models, one implementing a load/store architecture, the other a symmetric architecture, are compared under identical simulation environments. The symmetric architecture instructions are more powerful, but also more complex; therefore the pipeline model for the symmetric architecture contains an additional stage with an additional adder, more bypasses, and an extra port to the register file. The authors' simulations show that the path length of the load/store architecture is 1.12 longer than that of the symmetric architecture. Nevertheless, most of this advantage is lost because of various pipeline delays that reduce the speedup factor from 1.12 to 1.0375. The main delaying contribution is due to resource dependency (0.064 CPI) and control dependency (0.048 CPI)

Published in:

Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on

Date of Conference:

28-31 May 1990