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A dual-core 64 b UltraSPARC microprocessor for dense server applications

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11 Author(s)
Takayanagi, T. ; Sun Microsystems, Sunnyvale, CA, USA ; Shin, J.L. ; Petrick, B. ; Su, J.
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A processor core, previously implemented in a 0.25 μm Al process, is redesigned for a 0.13 μm Cu process to create a dual-core processor with 1 MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise are discussed.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004