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The standard capacitance-voltage (C-V ) technique can no longer determine accurately the equivalent oxide thickness (EOT) for an advanced CMOS transistor with ultrathin gate dielectric where there is high gate leakage current, as well as series resistance; this situation will get worse as the CMOS transistor's scaling trend continues. This paper describes a simple methodology based on dual-frequency C-V measurement and four-element circuit model to extract accurately the EOT in the presence of gate leakage current and series resistance. This method can be effective with a current density of 1000 A/cm2 for a 10 μm ×10 μm capacitor. Such a high current density will satisfy the projected gate leakage current requirements for many generations of CMOS technologies, as specified in the 2003 International Technology Roadmap for Semiconductors.