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FPGA implementation of space-time block coding systems

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3 Author(s)
Baghaie A, M. ; Dept. of Electr. & Comput. Eng., Canterbury Univ., Christchurch, New Zealand ; Kuo, S. ; McLoughlin, I.V.

In this paper, the implementation of space-time block coding systems is discussed, particularly through the use of programmable logic such as FPGAs. The rationale for choice of such devices in preference to DSPs is discussed followed by an analysis of the design and development process and the methodologies employed in the design process. An example space-time system, time-reversal space-time block coding (TR-STBC) is discussed and implementation described.

Published in:

Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on  (Volume:2 )

Date of Conference:

31 May-2 June 2004

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