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Physical register inlining

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3 Author(s)
Lipasti, M.H. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Mestan, B.R. ; Gunadi, E.

Physical register access time increases the delay between scheduling and execution in modern out-of-order processors. As the number of physical registers increases, this delay grows, forcing designers to employ register files with multicycle access. This paper advocates more efficient utilization of a fewer number of physical registers in order to reduce the access time of the physical register file. Register values with few significant bits are stored in the rename map using physical register inlining, a scheme analogous to inlining of operand fields in data structures. Specifically, whenever a register value can be expressed with fewer bits than the register map would need to specify a physical register number, the value is stored directly in the map, avoiding the indirection, and saving space in the physical register file. Not surprisingly, we find that a significant portion of all register operands can be stored in the map in this fashion, and describe straightforward microarchitectural extensions that correctly implement physical register inlining. We find that physical register inlining performs well, particularly in processors that are register-constrained.

Published in:

Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on

Date of Conference:

19-23 June 2004