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"Extreme edge engineering" - 2 mm edge exclusion challenges and cost-effective solutions for yield enhancement in high volume manufacturing for 200 and 300 mm wafer fabs

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14 Author(s)
T. Tran ; Infineon Technol., Richmond, VA, USA ; W. Roberts ; J. Tiffany ; I. Jekauc
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Significant financial benefits are realized by reducing the wafer edge exclusion to gain additional productive chips as well as enhance the yield of the former edge-most region of the wafer. Challenges are discussed and cost-effective solutions provided for major unit process and integration issues such as plasma-etch induced blocked/distorted pattern, image displacement, interlayer misalignment, lithography edge coating and patterning, pattern-density-dependent CMP and Etch non-uniformity, scribe readability, and shared-driver shorts.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004