"Extreme edge engineering" - 2 mm edge exclusion challenges and cost-effective solutions for yield enhancement in high volume manufacturing for 200 and 300 mm wafer fabs

Significant financial benefits are realized by reducing the wafer edge exclusion to gain additional productive chips as well as enhance the yield of the former edge-most region of the wafer. Challenges are discussed and cost-effective solutions provided for major unit process and integration issues such as plasma-etch induced blocked/distorted pattern, image displacement, interlayer misalignment, lithography edge coating and patterning, pattern-density-dependent CMP and Etch non-uniformity, scribe readability, and shared-driver shorts.