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This paper describes a low-power write scheme which reduces SRAM power by 90% by using seven-transistor sense-amplifying memory cells. By reducing the bitline swing to VDD/6 and amplifying the voltage swing by a sense-amplifier structure in a memory cell, the charging and discharging component of the power of the bit/data lines is reduced. A 64-kb test chip has been fabricated and correct read/write operation has been verified. It is also shown that the scheme can also have the capability of leakage power reduction with small modifications. Achievable leakage power reduction is estimated to be two orders of magnitude from SPICE simulation results.