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An eight-bit divider implemented in asynchronous pulse logic

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3 Author(s)
M. Nystrom ; Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA ; E. Ou ; A. J. Martin

Asynchronous pulse logic (APL) is an adaptation of quasi delay-insensitive (QDI) techniques using easily controllable timing assumptions that speed up the handshakes without changing the high-level dataflow model. We review the basic properties of APL circuits and techniques for describing them in and compiling them from a higher-level representation. We describe a reasonably complex test chip consisting of an 8-bit integer divider. Finally, we describe performance results from low-level SPICE simulations of the test chip. The results show that it is possible to design, with a high degree of automation, complex systems with a throughput of 10 CMOS transitions (less than 15 F04 delays) per cycle.

Published in:

Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on

Date of Conference:

19-23 April 2004