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Delay model has a great impact on asynchronous circuits. The scalable-delay-insensitive (SDI) model is based on the variation factor K that represents the degree of variation in an approximately scalable delay distribution. If the scaling variation is expected to be large, larger K value is used in the SDI model based synthesis and layout. K value is decided by the technology and the operating environment. We show some evaluation results for the scaling ratio of circuit components and scaling variation between any two components in the circuit using SPICE simulation. Then we present how to decide K value and show some evaluation results of the variation factor K for different technologies. Finally, as a case study we show how to design a delay line for the SDI model based bundled-data circuits.