Architectural design features of a programmable high throughput AES coprocessor

Programmable, high throughput domain specific crypto processors are required for different networking applications. We present the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18 /spl mu/m CMOS technology without any penalty in throughput for any of the above modes.