A new low switching noise CMOS logic circuits for single-chip CMOS imaging system

In this paper, we present a new low switching noise CMOS logic for on-chip CMOS image sensors, which reduce the switching noise through the substrate. The instantaneous peak current in digital system is the main source of the substrate noise and the injected current noise propagates through highly doped substrate and contaminates the sensitive image sensing systems. AMI 0.5 /spl mu/m CMOS technology is used for the analysis of switching noise. Simulation results show that the proposed logic generates lower ground bounce compare to the other low noise logic circuits. As a result it enables system-on-chip CMOS imaging system to be less susceptible to switching noise than when using other low noise logics.