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Algorithmic Aspects of One-Dimensional Layout Compaction

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2 Author(s)
J. Doenhardt ; Universitat-Gesamthoschule-Paderborn, Paderborn, Germany ; T. Lengauer

We present a theory of one-dimensional layout compaction that is based on the graph theoretic approach used in such compacters as reported in [5], [7], [11], and [26]. Compaction here consists of two steps. In the first stage, a directed graph is extracted from the layout. In the second stage, compaction is performed by solving a single-source shortest path problem on this graph. The paper presents new efficient algorithms and/or heuristics for the first stage of the compaction process. A compacter based on the framework presented here that incorporates the algorithms described is a powerful tool that can easily be tailored to specific applications. It allows a tradeoff between the space and runtime performance of the compacter and the quality of the compaction.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 5 )