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This paper proposes a new representation of nets for gate matrix layout, called dynamic-net-lists. The dynamic-net-list representation is better suited for layout optimization than the traditional fixed-net-list since with it net-bindings can be delayed until the gate-ordering has been constructed. Based on dynamic-net-lists, an efficient modified min-net-cut algorithm has been developed to solve the gate ordering problem for gate matrix layout. This new approach is shown through theoretical analysis and experimental results to reduce the number of horizontal tracks and hence the area significantly. The time complexity of the algorithm is O(N log N), where N is the total number of transistors and gate-net contacts. It is also shown that an ideal min-net-cut algorithm for optimal gate matrix layout with n gate signals is at worst a log-n approximation algorithm and is conjectured to be a relative approximation algorithm.