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Fast Methods for Switch-Level Verification of MOS Circuits

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2 Author(s)
Reeves, D.S. ; Department of Computer Science, North Carolina State University, Raleigh, NC, USA ; Irwin, M.J.

Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:6 ,  Issue: 5 )