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This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal arithmetic weight. These circuits consist of full and half adders interconnected in an iterative manner defined by the counting process. The general class of counter circuits contain reconvergent fanouts and are not as structurally regular as one- or two-dimensional iterative logic arrays. A model for analyzing the structure of counter circuits is proposed. Several schemes for generating test sets that exploit the iterative structure of counter circuits are presented. The testability of such circuits is enhanced by imposing certain design constraints on them. Some methods for generating easily testable counter circuits are proposed. It is shown that counter circuits can always be designed to be testable with either eight or ten tests, irrespective of the input size.