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Scaling planar silicon devices

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8 Author(s)
Ching-Te Chuang ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Bernstein, K. ; Joshi, R.V. ; Puri, R.
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The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.

Published in:

Circuits and Devices Magazine, IEEE  (Volume:20 ,  Issue: 1 )