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An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures

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2 Author(s)
K. Srinivasan ; Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA ; K. S. Chatha

System-level low power scheduling techniques are required for optimizing the performance and power of embedded applications that are mapped to multiprocessor System-on-Chip (SoC) architectures. In this paper, we present an integer linear programming (ILP) formulation that combines loop transformations (pipelining and unrolling) and system-level low power optimization techniques (dynamic voltage scaling (DVS) and power management (DPM)) to minimize the power consumption, while satisfying the period and deadline constraints of the application. We also present three modifications that relax one or more constraints in the optimal formulation in order to obtain smaller run times. We present experimental analysis by applying the formulations on an MPEG decoder algorithm. All results are compared against two existing techniques. Our formulations result in large system-level power reductions (max: 48.2%, min: 15.92%, avg: 31.9%). The modified ILP formulations result in exponential decrease in runtimes, and a corresponding linear degradation in the result quality.

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VLSI Design, 2004. Proceedings. 17th International Conference on

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