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On whitespace and stability in mixed-size placement and physical synthesis

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3 Author(s)
Adya, S.N. ; Dept. of Electr. & Eng. Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Markov, I.L. ; Villarrubia, P.G.

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool. In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis. In the context of earlier proposed techniques for mixed-size placement, we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, data paths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.

Published in:

Computer Aided Design, 2003. ICCAD-2003. International Conference on

Date of Conference:

9-13 Nov. 2003