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Exploring efficient operating points for voltage scaled embedded processor cores

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3 Author(s)
M. Buss ; Dept. of Comput. Sci., California Univ., Irvine, CA, USA ; T. Givargis ; N. Dutt

Portable and battery operated devices pose a unique design challenge in terms of performance requirements, low-power constraints, and short design cycles. Embedded soft cores, on the other hand, provide functional flexibility and guarantee rapid design and thus are gaining popularity in designing such portable and battery operated devices. To address the low power needs, dynamic voltage scaled (DVS) processors provide a new tradeoff dimension to the designer. This work proposes an application-specific design space exploration framework for selecting energy-efficient operating points in an embedded soft core. Specifically, we address the problem of selecting an appropriate number of operating voltage/frequency points and the distribution of these points along the valid voltage span of a processor, given the application that is to be executed on the processor. Furthermore, we provide a static intra-task scheduling technique that reduces energy consumption (4-20% in our experiments) even when the worst-case application execution time does not leave any slack for effective voltage scaling. We have experimentally verified our technologies on a large set of embedded benchmarks selected from MiBench, PowerStone, and MediaBench.

Published in:

Real-Time Systems Symposium, 2003. RTSS 2003. 24th IEEE

Date of Conference:

3-5 Dec. 2003