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This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-μm logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 μW owing to the hierarchical power supply and SSR. The macro size is 4.59 mm2. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.
Date of Publication: Nov. 2003