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This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-μm CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10-12 while consuming 540 mW from a 1.8-V supply.
Date of Publication: Nov. 2003