Cart (Loading....) | Create Account
Close category search window
 

A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ranganathan, N. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Murugavel, A.K.

We investigate the problem of dynamic power optimization through gate sizing and voltage scaling under a given delay constraint. Several algorithms have been proposed in the literature to handle gate sizing and voltage scaling independently or together with the goal of satisfying certain power budget constraints without affecting the timing constraints. Decentralized algorithms have been proposed in the literature for distributing a divisible resource among the components of the system. We formulate the problems as economic models that attempt to distribute the delay among the gates of the circuit such that the dynamic power of the circuit is optimized. Since, optimizing all the gates in the circuit at the same time can be computationally intensive, the gates in a given path are handled together. The circuits are represented as economic models and mathematical formulations are developed which are further transformed as game theoretic models for which Nash equilibrium based solutions are investigated. Thus, the main contribution of this work is the application of microeconomic models and game theory for these VLSI CAD problems. Models are developed for the gate sizing, voltage scaling and simultaneous gate sizing and voltage scaling problems. The algorithms are iterative, fast, simple and can lead to rapid convergence. Competition among the gates can provide the best overall optimization. In the proposed algorithms, the gates compete against each other to optimize their power consumption and hence that of the entire circuit. The proposed solutions yield better power optimization than other methods as shown in the experimental results for MCNC '91 benchmark circuits.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.