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Automatic generation of critical-path tests for a partial-scan microprocessor

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4 Author(s)
Grodstein, J. ; Intel Corp., Shrewsbury, MA, USA ; Bhavsar, D. ; Bettada, V. ; Davies, R.

We present our experiences generating scan-based critical-path tests for the partial-scan Alpha 21364 microprocessor, including the effects of crosstalk and multiple-inputs switching on path delay. Insufficient scan penetration made this difficult [D.Bhavsar (2002)], but a new ATPG algorithm increased our coverage. Comparison with actual silicon shows interesting results; we explain them with statistical analysis, factoring the effect of statistical process variation into the effects of crosstalk and multiple-input switching on delay. Finally, we draw conclusions about how to help make future designs amenable to speed testing.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003