Referenced Items are not available for this document.
A global clock network comprised of coupled, standing-wave oscillators is prototyped in a 0.18μm 6M CMOS process. The clock network operates from 9.8 to 10.5 GHz with 0.6ps skew and contributes only 0.5ps jitter when referencing a clock source with 1.4ps rms jitter.
Published in:
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Date of Conference: 2003
- Page(s):
- 428 - 504 vol.1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-7707-9
- INSPEC Accession Number:
- 7791713
- Digital Object Identifier :
- 10.1109/ISSCC.2003.1234369
- Product Type:
- Conference Publications
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