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Cascaded PLL design for a 90nm CMOS high performance microprocessor

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8 Author(s)
K. L. Wong ; Intel Corp., Hillsboro, OR, USA ; E. Fayneh ; E. Knoll ; R. H. Law
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PLL clock generators are designed for a third-generation NetBurst/spl trade/ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into account a dual-sloped VCO control. A new charge pump topology offers superior symmetry.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003