Skip to Main Content
A three-level clock distribution design for a next generation IA microprocessor is implemented in a 1.2V, 90nm process that scales to a 5GHz range. It achieves sub-10ps global clock uncertainty and addresses in-die variation, RLC delay matching, and scalability with die size and process issues without additional clock jitter or layout area. Risk management of practical constraints due to schedule, changing floor plan, loading and process are discussed.
Date of Conference: 2003