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A 97M transistor custom-designed network processor integrating 16 VLIW CPUs implements the Cisco Toaster instruction set at 600 MHz in a 0.18 μm process. The chip area is 349 mm2 and consumes 20 W at 500 MHz. The frequency is 2.5× that of an ASIC Toaster implementation in a similar process.
Date of Conference: 2003