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A 1.5 GHz third generation Itanium/spl reg/ processor

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2 Author(s)
J. Stinson ; Intel, Santa Clara, CA, USA ; S. Rusu

A third-generation 1.5 GHz Itanium/spl reg/ processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6 MB, 24-way set associative L3 cache. The 374 mm/sup 2/ die contains 410M transistors and is implemented in a dual-V/sub T/ 0.13 /spl mu/m technology having 6-level Cu interconnects with FSG dielectric and dissipates 130 W.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003