Referenced Items are not available for this document.
A 40/43 Gb/s SONET OC-768 4:1 MUX/CMU is implemented in a 120 GHz fT SiGe BiCMOS process. When co-packaged with a companion 16:4 multiplexer, the chip produces less than 3 ps of pattern dependent jitter and 175 fs RMS random jitter. A packaged BER of better than 10-14 is measured with 231-1 PRBS data inputs. The chip consumes 4.9 W from 1.8 V and -5.2 V supplies.
Published in:
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Date of Conference: 2003
- Page(s):
- 236 - 237 vol.1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-7707-9
- INSPEC Accession Number:
- 7785759
- Digital Object Identifier :
- 10.1109/ISSCC.2003.1234282
- Product Type:
- Conference Publications
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