Referenced Items are not available for this document.
A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-V00 signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
Published in:
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Date of Conference: 2003
- Page(s):
- 186 - 487 vol.1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-7707-9
- INSPEC Accession Number:
- 7785746
- Digital Object Identifier :
- 10.1109/ISSCC.2003.1234260
- Product Type:
- Conference Publications
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