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1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

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6 Author(s)
K. Kanda ; Inst. of Ind. Sci., Univ. of Tokyo, Japan ; D. D. Antono ; K. Ishida ; H. Kawaguchi
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A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, return-to-half-V/sub 00/ signaling and sense amplifying F/F. The measured test chip fabricated in 0.35/spl mu/m CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003